Topic 3: The Memory System
4th Course in Telecommunications Engineering
Department of Computer Engineering and Telecommunications
Higher Polytechnic School
Contents
6.1 .- Memory hierarchy system.
6.2.- The cache memory.
Principles of operation. Organization.
Schemes of operation.
Substitution Algorithms.
6.3 The Virtual Memory System
Virtual Addressing: Paging and Segmentation
The Memory Management Unit (MMU): Functioning of the TLB
6.4.- Mechanisms to improve the memory system
Multilevel cache
Virtual cache vs real cache
Examples: The current microprocessor cache unit
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Technology of memory devices
Why should the memory system be improved?
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CPU
μProc
60% / year
(2x / 1.5year)
Gap performance
Processor-Memory
(↑ 50% / year)[19659002] DRAM
DRAM
9% / year
(2x / 10 years)
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Technology of memory devices
How can a memory system be improved?
Organizing a memory hierarchy
Memory cache (level L1, L2, L3 )
Applying the concept of virtual memory
MMU and TLB
Designing more efficient CPU / MEM connection systems
with the aim of obtaining transfer data to
maximum speed
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Memory hierarchy system
Cache
KBytes
~ 2-5 ns
10-2-10-3 $ / bit
Main Memory
Capacity
Access Time
Cost
GPR
100's Bytes
~ 1 ns
MBytes
~ 10-20 ns
10-5-10-6 $ / bit
Disk6
GBytes
~ 5-10 ms
10-7- 10-8 $ / bit
Tape
TBytes
~ sec-min
10-10 $ / bit
Top level
Manager
Transfer unit.
GPR
Instr./Data
Cache
Blocks
Memory
Pages
Disk
Files
Tape
Lower Level
Prog./Comp.
] 1-8 Bytes
Control cache
8-128 Bytes
Sist. operative
512-4kBytes
User
MBytes
Fastest
Largest
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System memory hierarchy
What is a memory hierarchy based on?
The principle of Locality:
Programs access a relatively small portion of the
address space at any instant in time
] There are two different types of locations:
Temporary Location: Codes and data recently accessed,
have a high probability of being accessed again in the near future
.
Space Locality: If a code or data is referenced, codes or
data whose memory addresses are close to the previous one,
will tend to be referenced soon.
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Yes Hierarchy of memory hierarchy
What should be taken into account when designing a hierarchy of
memory?
Where to place a block in the upper level?
How to find a block if it is at the top level?
Which block should be replaced in case of failure?
What strategy should be followed when modifying (writing) a block in
the upper level?
CPU
To the CPU [19659002] CPU
Memory
Top level
Blk X
Blk Z
Memory
Lower level
Blk X
Blk Y
Blk Z [19659002] Blk K
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The cache memory
Definitions:
Cache: Invisible memory, very fast and small in size the processor and the memory
H, hit rate:% of references to memory that are in the cache.
F, frequency of failures (Miss rate):% of references to memory that are not in the cache.
main.
F = 1-H
tc, Access time to the cache: time needed to access a cache data.
tB, penalty for failure: time needed to replace a block from the lower level ,
includes the time to take it to the processor.
The average access time to the memory system is:
A failure in the cache INCREASE the execution time
(
of the instruction involved
= NI
T
×
CPU
t
acc
1 (- + =
t
c
tH
) [19659002] B
CPI + CD M) T
×
CYCLE
CD M = A ccesses M emia
NI
×
Freq. failures
×
Penalty
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The cache memory. Principles of operation
Address
CACHE
Directory
Blocks
CPU
U.Control
Data
MEMORIA
PRINCIPAL
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The cache memory. Principles of operation
Directory cache
Carried out in associative memory or CAM memory (Content
AddressableMemory).
Indicates whether the data requested by the processor is in the
cache. If hit (match) it indicates the address of the block where
finds the data.
Cache blocks
Carried out in SRAM memory
Each block contains a certain number of bytes to which
is accessed in the case of a successful cache.
Control unit
Generates the control signals for the operation of the unit
cache
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The cache memory. Organization
Cache Completely Associative
LABEL BITS
BYTE EN
BLOCK
ADDRESS
DIRECTORY
BLOCKS
If Success,
data to CPU
= ?
=?
=?
=?
=?
Right? ó ¿Fallo?
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The cache memory. Organization
Example: Cache complet. associative 512 Bytes, 8By / block
29b
0045FF3 0
64 comp.
F
A
F
F
F
DIRECTORY
54445F0 0
0045FF3 0
0045FF3 1
6632FF3 1
F045FF3 0
Right? or Fail?
3b
100
ADDRESS (32 b)
0045FF34
BLOCKS
100
0F FA 00 FF 33 AA 0F 22
0FFA0 … ..A0F22
CPU
FF00FA0F
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The cache memory. Organization
Cache of direct correspondence (Associative of 1 way)
BITS OF LABEL
BITS OF INDICE
BYTE IN
BLOCK
ADDRESS
DIRECTORY
BLOCKS
=?
Right? or Fail?
Si Acierto,
data to CPU
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The cache memory. Organization
Example: Direct correspondence cache of 4kB and 16 By / Bloq
20b
FA067
8b
04
4b
C
ADDRESS (32 b) [19659002] FA06704C
DIRECTORY
00
BLOCKS
C
A
FF
FA067
2F 3D 00 A0
FF
A0
25 7F
2F3D0 … 0257F
CPU
A0003D2F
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The cache memory. Organization
Associative cache by way (N tracks)
LABEL BITS
INDEX BITS
BYTE IN
BLOCK
VIA-1
DIRECTORY BLOCKS
VIA-N
DIRECTORY BLOCKS
ADDRESS
If Success, extracts
data from BL-1 or BL-N
and sends it to the CPU
BL-1
BL-N [19659002] =?
Right? or Fail?
=?
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The cache memory. Organization
Example: Cache of 4kB with 64 By / Block and 4-way associative
22b
AFA64 00
4b
1100
6b
00 8
ADDRESS ( 32 b)
AFA64308
VIA-1
VIA-2
VIA-3
VIA-4
3FAA ….
AFA64 00
257A .. ..
46FF ….
452DD3FF … 48 Bytes … 4356FFCD3D3F4F3D00A03420
001000
CPU
CDFF5643
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1100
0
F
The cache memory. Organization
Cache Correspondencia Directa VS Associative by N Vías
CD needs 1 comparator AV needs N comparators
CD can obtain the data before a success or failure occurs. AV
has the data only after the comparison, you need to insert a
multiplexer to select the data of the path in which the
success occurs.
What mission do the validity bits have? (BV)?
If there is 1 BV for each block ⇒ In case of success if BV = '0', block no
contains valid data.
If there is 1BV for each word in the block ⇒ If successful, the word
with BV to '0' does not contain valid data.
What mission has the modification or dirt bit (M)?
Always associated with a block. If M = '1' ⇒ there has been at least one
writing in the cache that has not been written in memory.
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] The cache memory. Operating schemes
Capture operations
Demand capture: A block (whole or part) is loaded only when
references a piece of data contained in it and a fault occurs.
Anticipatory capture: A block (integer) is loaded before being
referenced.
Selective capture: A data whose reference has
originated a failure is not always loaded. Example: "non-cacheable" addresses
Memory write and update operations
Direct Write (ED) (WriteThrough): Writes to the time in the cache and
in the main memory.
Two Strategies: EDAE and EDSAE.
Post-Write (PE) (WriteBack): The main memory is updated, only
when replacing a block. Two modalities depending on the bit M.
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The cache memory. Schemes of operation
1.- ED and PE: Operation of CONCERT in reading
Address
CACHE
Directory
Blocks
CPU
U.Control
Data [19659002] MEMORY
MAIN
Cache⇒CPU
AL = (H) (1 w) tC
t acc
–
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The cache memory. Operation diagrams
2.- ED: Operation of FAULT in reading
Address
CACHE
Directory
Blocks
CPU
U.Control
Data
MEMORY
MAIN
FL = (1- H) (1 w) t C
t acc
Cache⇒CPU
–
MEM⇒Cache
–
+ ( 1- H) (1 w) t B
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The cache memory. Operating diagrams
2.- PE: Operation of FAILURE in reading
Address
CACHE
Directory
Blocks
CPU
U.Control
Data
MEMORY
MAIN
FL = (1- H) (1 w) t C
t acc
Cache⇒CPU
–
Cache⇒MEM
–
+ ( 1- H) (1 w) w tM B
MEM⇒Cache
–
+ (1- H) (1 w) t B
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