Programming PDF – Unit 2 Intel 80×86 Programming Model

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Unit 2

Programming Model

of Intel 80×86

SYSTEMS BASED ON MICROPROCESSORS

Degree in Computer Engineering

EPS – UAM

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Index

2. Intel 80×86 programming model.

Family 80×86 as a particular case.
Internal records and architecture of 80×86.

2.1.
2.2
2.3. Access and organization of memory.
2.4. Addressing modes.
2.5. Directives and operators of the 80×86 assembler.
2.6. Structure of an assembler program
2.7.
2.8. Memory map of the PC system
2.9

Assembly instructions

Interrupts: mechanism and interruption vectors

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2.1. Family 80×86 as a special case

Microprocessors appear in the 70 (1971- …) with 4 bits
and then 8 bits (8085 with 64KB of memory).

Invented by Intel as digital integrated circuits and
programmable to replace wired digital circuits.

Family 80×86 was born in 1978 with 8086 (16 bits and 1 MB
memory). Continues with: 80186, 80286, 80386, 80486, …

Parallel appears 8088 (IBM personal computer or
PC): 8086 8-bit.

Initial Competitor: Motorola 6800 (8 bits) and 68000 (16 bits).

Intel guarantees compatibility of its microprocessors
from the beginning and introduces memory segmentation
(64 KB segments)

CISC technology vs. RISC (most current)

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2.2. Internal records and architecture

of 80×86 (I)

AH
BH
CH
DH

AL
BL
CL
DL

SP
BP
YES
DI

REG. TEMPORARY

ALU

REG. FLAGS

RECORDS
GENERAL

BUS DATA ALU

(16 BITS)

UNIT

EXECUTION

(EU)

BUS ADDRESSES (20 BITS)

SUMATOR [19659002] BUS DATA

(16 BITS)

CS
DS
SS
ES

IP

OTHER REG.

COLA

INSTRUCTIONS

BUS [19659002] MUX

LOGIC
CONTROL

DEL
BUS

EXECUTION UNIT

INTERFACE UNIT WITH BUS

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2.2. Internal registers and architecture

of 80×86 (II)

Data records

AX (AH-AL), BX (BH-BL), CX (CH-CL), DX (DH-DL)

] (2)

2.2. Internal records and architecture

of 80×86 (III)

Data records

AX (AH-AL), BX (BH-BL), CX (CH-CL), DX (DH-DL)

] Act as accumulators in instructions of
transfer, logical and arithmetic.
Each of 16 bits, divisible into 2 registers of 8 bits.
Specific tasks in some cases (for any
use if they are free):

AX: Multiply, split and I / O operations.
BX: Base register for indirect addressing

(points to the base of a table)

CX: Loop counter.
DX: Multiply, divide, I / O operations.

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2.2. Internal registers and architecture

of 80×86 (IV)

Leading registers: SP, BP, SI, DI

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2.2. Internal registers and architecture

of 80×86 (V)

Leading registers: SP, BP, SI, DI

Involved in memory addressing as
shifts (offsets) with respect to the areas of
memory indicated in segment registers.
SP (Stack Pointer): Used next to segment register
of SS stack. Involved in:
Calls to subroutines
Interrupts
Battery management instructions

BP (Base Pointer): Used next to segment register
SS stack. Useful for accessing the parameters of
passed subroutines per stack.
SI (Source Index): Used to index tables in
memory (reading). For any use if it is free.
DI (Destination Index): Used to index tables in
memory (writing). For any use if it is free.

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2.2. Internal records and architecture

of 80×86 (VI)

Segment records: CS, SS, DS, ES

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2.2. Internal registers and architecture

of 80×86 (VII)

Segment registers: CS, SS, DS, ES

Involved in memory addressing indicating
zones of 64KB of memory (segments).
] CS (Code Segment): Indicates the code segment
machine (program). Together with the pointer of
IP instructions constitutes the program counter.
SS (Stack Segment): Indicates the stack segment. Together
with SP or BP indicates an absolute memory location
on the stack.
DS (Data Segment): Indicates the main segment of
data (global variables).
ES (Extra Segment): Indicates the additional segment of
data (global variables).

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2.2. Internal registers and architecture

of 80×86 (VIII)

Register instruction pointer: IP

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2.2. Internal registers and architecture

of the 80×86 (IX)

Register instruction pointer: IP

Indicates the offset (offset) within the segment
indicated by CS where the following
code instruction is found machine to be executed
(program counter).

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2.2. Internal registers and architecture

of the 80×86 (X)

State Register (FLAGS)

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2.2. Internal registers and architecture

of the 80×86 (XI)

State register (FLAGS)

Some of its 16 bits indicate status information
of the processor and the last operation of the ALU.

15

14

13

12

11
10
OF DF

8
9
IF TF

7
6
SZ

5

3

4
AC

2
P

1

0
C

IF: interrupt bit
DF: address bit
OF: overflow bit

Z: bit zero
S: sign bit
TF: trap bit

C: carry bit
P: bit parity
AC: auxiliary carry bit

The flags (flags) C, AC, S, P, Z and OF depend on the result
of the last operation executed by the ALU.
The IF flag Enables or disables hardware interrupts.
The TF flag enables or disables execution "step by step"
The DF flag increments or decrements the index pointers in
string instructions.
All bits can be set to 0 or 1 with specific instructions
.

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2.3. Access and organization of memory (I)

Physical memory of a system based on 8086 organized
as 220 1-byte (1 MB) positions.
1 MB physical memory divided at logical level in
] "Segments" of 64 KB.
The segments start in multiple directions of 16.
Two consecutive segments are separated by 16 bytes.
In a program, the instructions are usually in a
segment, the data in one or several different segments and
the stack in another (there are cases in which this is not fulfilled).
The CPU you can access up to four different segments
at the same time (CS, DS, ES and SS records with different values).
There can be total or partial overlapping of segments
(extreme case: CS, DS, ES and SS with same value.)
The program can change the value
of the segment registers at any time.

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2.3. Access and organization of memory (II)

Access to memory (real mode)
Hardware: 20 bits of address (A19-A0)
Software: 32 bits (16 bits of Segment and 16 bits of Offset )

PHYSICAL ADDRESS = Segment x 16 + Offset

Bit 19

Bit 15

Bit 0

16 x

+

SEGMENT

SEGMENT

0 [19659002] 0

00

OFFSET

PHYSICAL ADDRESS

(2) 2.3. Access and organization of memory (III)

1 byte

00000h

Address plus
segment low

Register
segment

Offset

Address accessed

FFFFFh

64 KB
Maximum size
of the segment

(2) 2.3. Access and organization of memory (IV)

Examples of access to memory (real mode)

(offset)

CS = A783h (segment)
IP = 403Eh
Physical address = A783h x 16 + 403Eh =
A783h x 10h + 403Eh =
A7830h + 403Eh = AB86Eh

ES = 54A3h (segment)
DI = 1F2Bh
Physical address = 54A30h + 1F2Bh = 5695Bh

(offset)

SS = 4675h
SP = A001h
Physical address = 46750h + A001h = 50751h

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2.3. Access and organization of memory (V)

Access to memory from programs

Access can be to a byte or two consecutive
(one word) according to the record that intervenes in the
instruction.
Example: if the
following instructions were previously executed:

mov AX, 2000h
mov DS, AX
the result of the following
operations is:
mov AX, [455h]
mov AX, [456h]
mov AH, [457h]
mov AL, [458h]

; AX = 2F32h
; AX = 952Fh
; AH = 95h
; AL = E4h

20455h

20456h

20457h

20458h

20459h

32

2F

95

E4

FB

(2) [19659002] 2.4. Addressing modes (I)

Seven addressing modes:

Immediate
Per registration
Direct
Indirect
Relative
Indexed
Implicit

Direct modes e indirect consist of
"pointers" to memory.

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2.4. Addressing modes (II)

Immediate addressing
The source operand is always a value and the destination is a

record.

Examples:

mov CL, 3Fh
mov SI, 4567h [19659002]; 3Fh ⇒ CL
; 4567h ⇒ YES

Address by record
Both operands are always registers.

Examples:

mov DX, CX
mov BH, CL

; CX ⇒ DX
; CL ⇒ BH

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2.4. Addressing modes (III)

Direct addressing
The offset of the memory location you want

to access is specified in the instruction. By default, the
segment is indicated by DS.
Examples if DS = 3000h:

mov DX, [678Ah]; load in DL the content of position

mov AL, [32h]

mov [800h] BL

; of memory 3678Ah and in DH on
; content of the memory location
; 3678Bh.
; load in AL the content of the position
; memory 30032h
; load in memory location 30800h
; the content of BL.

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2.4. Addressing modes (IV)

Indirect addressing by record
The effective address of the operand is contained in one

of the BX, BP, SI, or DI registers.

Example:

mov AX, [BX]

Relative addressing to base
The effective address is obtained by adding a

displacement to the BX register or BP.

Equivalent examples if offset of the TABLE is 4:

mov AX, [BX] +4
mov AX, 4 [BX]
mov AX, TABLE [BX]
mov AX, [BX+4]

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2.4. Addressing modes (V)

Indexed addressing
The effective address is calculated by adding a

offset to the SI or DI content.

Equivalent examples if the offset of the TABLE is 4:

mov AX , [SI] +4
mov AX, 4 [SI]
mov AX, TABLE [SI]
mov AX, [SI+4]

Addressing indexed to base
The effective address is obtained by adding BX or BP to SI

or DI and / or a direct offset.

Examples:

mov AX, TABLE [BX] [SI]
mov AX, TABLE + [BX] + [SI]

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2.4. Addressing modes (VI)

Relative addressing
Used in conditional jumps: The operand is an
signed 8-bit shift (-128 to 127)
that is added to the IP instruction pointer.
Examples:

jnc 26
jz label

; if the label is at a distance
; greater than or equal to -128 and less than 128

Implicit addressing
It is not necessary to indicate the operand (it is implicit).

Examples:

cli
stc

; sets the interrupt flag to 0
; p

.

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