Unit 5
Entry / Exit
SYSTEMS BASED ON MICROPROCESSORS
Degree in Computer Engineering
EPS – UAM
(5)
Index
5. Input / Output
Input and Output Programming Techniques (I / O).
Probe.
Interruption.
5.1.
5.2.
5.3.
5.4. DMA.
5.5. Management and programming of interrupts in
80×86: the programmable interrupt controller
8259A.
(5)
5.1. I / O Programming Techniques (I)
A microprocessor-based system must transfer
data from (input) and to (output) external devices.
Three ways to perform the transfer:
Probe (survey, polling)
The CPU is responsible for sending and receiving data, and the
synchronization with the peripheral (wait for the arrival of data or
wait for the request to send data).
Interruption
The CPU is responsible for sending and receiving data.
The synchronization is performed by hardware interrupts
that the CPU receives.
DMA (Direct Memory Access)
The CPU configures a controller for the CPU. DMA that handles
sending and receiving data.
The synchronization is performed by the DMA controller itself
by means of hardware interrupts.
Used for block transfer.
(5)
5.1. I / O Programming Techniques (II)
Each peripheral is accessed by the CPU through a
I / O port (controller) acting as an interface.
The CPU usually accesses the ports reading and writing
internal registers (each register has an I / O address):
Input registers: Data from the peripheral to the CPU.
Output registers: Data from the CPU to the peripheral.
State records: Current status of the peripheral.
C
P
U
S
O
T
A
D
S
U
B
L
OR
R
T
N
OR
C
S
U
B
Port E / S
Reg. Entry
0011..110
Reg. Output
111001..1
Reg. State
1
1
I
P
E
R
F
E
R
C
O
I [19659004] S
E
N
O
C
C
E
R
D
S
U
B
I
I
(5)
5.2. Probe (I)
The CPU has to send and receive data, and synchronize with the peripheral
.
Synchronization by active standby: a loop queries
continuously the status register (very inefficient).
Protocol of "handshaking" by
two control lines: NEW DATA E and NEW DATA S.
I
I
S
E
N
OR
C
C
E
R
D
] S
U
B
S
O
T
A
D
S
U
B
L
OR
R
T
N
O
C
S
U
B
Reg. Entry
0011..110
Reg. Output
111001..1
Reg. State
NEW DATA E
1
1
NEW DATA S
I
P
E
R
F
É
R
C
O
I
(5)
5.2. Probe (II)
Basic protocol for writing data to the peripheral:
CPU writes data in output register.
CPU activates signal NEW DATA S in status register.
CPU waits for signal activation NEW DATA E in register of
status (active wait).
Peripheral receives data from port and activates signal NEW DATA E
(Acnowledge, ACK).
I
S
E
N
O
C
C
E
R
D
S
U
B
I
S
O
T
A
D
S
U
B
L
OR
R
T
N
O
C
S
U
B
Reg. Entry
0011..110
Reg. Output
111001..1
Reg. State
NEW DATA E
1
1
NEW DATA S
I
P
E
R
F
É
R
C
O
I
(5)
5.2. Polling (III)
Basic protocol for reading data from the peripheral:
CPU waits for signal activation NEW DATA E in register of
status (active wait).
Peripheral sends data to port and activates signal NEW DATA E.
CPU reads data from input register
CPU activates signal NEW DATA S in status register.
I
I
S
E
N
O
C
C
E
R
D
S
] U
B
S
O
T
A
D
S
U
B
L
O
R
T
N
O
C
S
U
B
Reg. Entry
0011..110
Reg. Output
111001..1
Reg. State
NEW DATA E
1
1
NEW DATA S
I
P
E
R
F
É
R
C
O
I
(5)
5.2. Polling (IV)
Example: Reading data
from I / O port,
storing them in
memory buffer and with
sending control byte.
Port of E / S:
52h ⇒ @ Reg.Entry
53h ⇒ @ Reg.Exit
54h ⇒ @ Reg.State
data SEGMENT
buffer 200 DUP (0)
data ENDS
code SEGMENT
………
mov ax, data
mov ds, ax
mov si, 0
wait: in al, 54h; Active wait
test at, 00000001b
jz wait
in al, 52h; Reading of data
mov buffer [ si ] to
inc si
cmp yes, 200
jne wait
mov al, 0FFh
out 53h, al; Control byte
(5)
5.3. Interruption
The CPU is interrupted when peripheral sends data
(input) or when it sends request for reception of
data (output).
The CPU executes a service routine that reads data or
sends data through the port registers.
I
I
S
E
N
O
C
C
E
R
D
S
U
B
L
OR
R
T
N
OR
C
S
] U
B
S
O
T
A
D
S
U
B
PIC
Reg. Entry
0011..110
Reg. Output
111001..1
Reg. State
1
Reg. Interrupts
1
NEW
DATA S
NEW
DATA E
I
P
E
R
F
É
R
C
O
I
C
P
U
INT
INTA
(5)
5.4. DMA (I)
The CPU programs the DMA driver so that
transfers a block of data from memory to the I / O port
(output) or from the memory (input) port.
RAM Memory
I
I
S
E
N
O
C
C
E
R
D
S
U
B
D
M
A
DACK
DREQ
S
OR
T
A
D
S
U
B
L
OR
R
T
N
OR
C
S
U
B
Reg. Entry
0011..110
Reg. Output
111001..1
Reg. State
1
Reg. Interrupts
1
NEW
DATA S
NEW
DATA E
I
P
E
R
F
É
R
C
O
I
(5)
5.4. DMA (II)
The DMA controller interrupts the CPU when
has transferred an entire block.
The CPU executes a service routine that accesses the
block (entry) or generates a new block block (output) and
reprograms the DMA controller.
I
I
S
E
N
O
C
C
E
R
D
S
U
B
L
OR
R
T
N
OR
C
] S
U
B
S
O
T
A
D
S
U
B
PIC
D
M
A
INT
C
P
U
INT
INTA
(5)
5.5. Management and programming of the
interrupts in the 80×86 (I)
The hardware maskable interrupts are
managed by the programmable interrupt controller
(PIC) 8259.
A PIC has 8 inputs of interrupt and one output.
Multiple interrupts
maskable can be handled depending on the number of 8259
installed (1 on PC / XT, 2 on PC / AT and higher).
The CPU receives a single request interrupt by
part of the main PIC (master).
Each interrupt can be masked by
independent through 8259.
Different priority schemes
can be set on maskable interrupts .
(5)
5.5. Management and programming of the
interrupts in the 80×86 (II)
PIC-0 addresses: 20h, 21h (PC / XT, PC / AT and later)
PIC-1 addresses: A0h, A1h (PC / AT and later)
Interrupts: PIC-0 ⇒ 08h (IR0), …, 0Fh (IR7)
PIC-1 ⇒ 70h (IR0), …, 7Fh (IR7)
Data Bus (8 bits)
PIC-0
Master
IR0
IR2
INT
#INTA
TO CPU
CPU
+ Vcc
# SP / # EN
IR7
TIMER
KEYBOARD
PIC-1
Slave
IR0
RTC
INT
#INTA [19659002] # SP / # EN
COP
IR5
IR7
GND
CONNECTOR
EXPANSION
(Bus ISA)
7
Q
R
I
3
Q
R
I
5
Q
R
6
4
Q
Q
] R
R
PC / XT
I
I
I [19659002] 5
1
Q
R
I
4
2
1
1
1
1
Q
Q
Q
R
R
R
PC / AT
I
I
I
0
1
Q
R
I
(5)
5.5. Management and programming of the
interruptions in the 80×86 (III)
Request for interruption through the master PIC:
1. I / O port active request for interruption of
master.
Data bus (8 bits)
PIC-0
Master
IR0
IR2
INT
#INTA
TO THE CPU
OF THE CPU
+ Vcc
# SP / # EN
IR7
TIMER
KEYBOARD
PIC-1
Slave [19659002] IR0
RTC
INT
#INTA
# SP / # EN
COP
IR5
IR7
GND
(5)
5.5 . Management and programming of the
interruptions in the 80×86 (IV)
Request for interruption through the master PIC:
1. I / O port activates request for interruption of
master.
2. If interruption has sufficient priority, Master PIC
activates CPU interrupt request (INT signal).
Data Bus (8 bits)
PIC-0
Master
IR0
IR2
INT
#INTA
TO THE CPU
OF THE CPU
+ Vcc
# SP / # EN
IR7
TIMER
KEYBOARD
PIC -1
Slave
IR0
RTC
INT
#INTA
# SP / # EN
COP
IR5
IR7
GND
(5)
5.5. Management and programming of the
interrupts in the 80×86 (V)
Request for interruption through the master PIC:
1. I / O port activates request for interruption of
master.
2. If interruption has sufficient priority, Master PIC
activates CPU interruption request (INT signal).
3. If CPU accepts interruption, it activates acceptance signal
(signal #INTA) twice in a row.
Data Bus (8 bits)
PIC-0
Master
IR0
IR2 [19659002] INT
#INTA
TO THE CPU
OF THE CPU
+ Vcc
# SP / # EN
IR7
TIMER
KEYBOARD
PIC- 1
Slave
IR0
RTC
INT
#INTA
# SP / # EN
COP
IR5
IR7
GND
( 5)
5.5. Management and programming of the
interruptions in the 80×86 (VI)
Request for interruption through the master PIC:
4. In the second acceptance, master PIC writes number
of data bus interruption.
09h (KEYBOARD)
PIC-0
Master
IR0
IR2
INT
] #INTA
TO THE CPU
OF THE CPU
+ Vcc
# SP / # EN
IR7
TIMER
KEYBOARD
PIC-1
Slave
IR0
RTC
INT
#INTA
# SP / # EN
COP
IR5
IR7
GND
(5)
5.5 Management and programming of the
interruptions in the 80×86 (VII)
Request for interruption through the master PIC:
4. In the second acceptance, master PIC writes number
of interruption in data bus.
5. CPU gets interrupt vector and executes routine of
service (RSI).
09h (KEYPAD)
PIC-0
Master
IR0
IR2
INT
# INTA
TO THE CPU
OF THE CPU
+ Vcc
# SP / # EN
IR7
TIMER
KEYBOARD
PIC-1
Slave
] IR0
RTC
INT
#INTA
# SP / # EN
COP
IR5
IR7
GND
(5)
5.5. Management and programming of the
interruptions in the 80×86 (VIII)
Request for interruption through the master PIC:
4. In the second acceptance, master PIC writes number
of interruption in data bus.
5. CPU gets interrupt vector and executes routine of
service (RSI).
6. Before finishing, RSI sends end command of
interrupt (End Of Interrupt, EOI) to master PIC.
7. Master PIC terminates the request.
09h (KEYBOARD)
09h (KEYBOARD)
EOI
PIC-0
Master
IR0
IR2
INT
] #INTA
TO THE CPU
OF THE CPU
+ Vcc
# SP / # EN
IR7
TIMER
KEYBOARD
PIC-1
Slave
IR0
RTC
INT
#INTA
# SP / # EN
COP
IR5
IR7
GND
(5)
5.5 Management and programming of the
interrupts in the 80×86 (IX)
Request to interrupt through the slave PIC:
1. I / O port activates interrupt request of slave
.
Data Bus (8 bits)
PIC-0
Master
IR0
IR2
INT
#INTA
TO THE CPU
OF THE CPU
+ Vcc
# SP / # EN
IR7
TIMER
KEYBOARD
PIC-1
Slave [19659002] IR0
RTC
INT
#INTA
# SP / # EN
COP
IR5
IR7
GND
(5)
5.5 . Management and programming of the
interrupts in the 80×86 (X)
Request of interruption through the slave PIC:
1. I / O port activates interrupt request from
slave.
2. If interruption has sufficient priority, PIC
.
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